| Technology Family | ABT |
| Supply voltage (Min) (V) | 4.5 |
| Supply voltage (Max) (V) | 5.5 |
| Number of channels (#) | 4 |
| IOL (Max) (mA) | 64 |
| ICC (Max) (uA) | 250 |
| IOH (Max) (mA) | -32 |
| Input type | TTL-Compatible CMOS |
| Output type | 3-State |
| Features | Ultra high speed (tpd <5ns), Partial power down (Ioff), Over-voltage tolerant inputs, Power up 3-state |
| Rating | Military |
- Typical VOLP (Output Ground Bounce)
???<1 V at VCC = 5 V, TA = 25°C - High-Drive Outputs (–32-mA IOH, 64-mA IOL)
- Ioff and Power-Up 3-State Support Hot Insertion
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
The ?ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
