As integrated circuit feature sizes continue to scale well below 0.25 microns, activedevice counts are reaching hundreds of millions. The amount of interconnect among the devices tends to grow superlinearly with the transistor counts, and the chip area is often limited by the physical interconnect area. Due to these interconnect area limitations, the interconnect dimensions are scaled with the devices whenever possible [1.1] [1.2]. In addition, to provide more wiring resources, IC’s now accommodate numerous metallization layers, with more to come in the future [1.3].
These advances in technology that result in scaled, multi-level interconnects may
address the wireability problem, but in the process create problems with signal integrity and interconnect delay. We introduce some of these interconnect problems in the remainder of this chapter, then the seven chapters which follow describe in detail various solutions for these problems.