What is functional verification? I introduce a formal definition for
functional verification in the next chapter, “The Language of Design Verification,”
and explore it in depth in chapter 2, “Functional Verification.” For
now, let’s just consider it the means by which we discover functional logic
errors in a representation of the design, whether it be a behavioral model, a
register transfer level (RTL) model, a gate level model or a switch level
model. I am going to refer to any such representation as “the device” or “the
device-under-verification” (DUV). Functional verification is not timing verification
or any other back-end validation process.
Logic errors (bugs) are discrepancies between the intended behavior of
the device and its observed behavior. These errors are introduced by the
designer because of an ambiguous specification, misinterpretation of the
specification or a typographical error during model coding. The errors vary
in abstraction level depending upon the cause of the error and the model level
in which they were introduced. For example, an error caused by a specification
misinterpretation and introduced into a behavioral model may be algorithmic
in nature while an error caused by a typo in the RTL may topological.
How do we expose the variety of bugs in the design? By verifying it! The
device may be verified using static, dynamic or hybrid methods. Each class
is described in the following sections.