The PTN3310/3311 board utilizes two logic translator from the PTN
product portfolio– the PTN3311, a PECL to LVDS translator, and the
PTN3310– a LVDS to PECL translator. For more information on the
ICs, please, refer to their corresponding data sheets.
The board is designed for an optimum evaluation of both parts. With
the assemble or dissemble of some resistors, the board could
operate in the following modes–– PTN3311 driving PTN3310,
PTN3310 driving PTN3311, or both parts operating independently.
For the PTN3311 to drive the PTN3310, the input signal from the
pattern generator must be connected to SMA J1 and SMA J2, and
resistors R5 & R6, R13 & R14, and R15 & R16 must be mounted on
the board, while resistors R21 & R22, R7 & R9, and R8 & R10
should be disassembled. The output signal could be taken to the
oscilloscope via SMAs J7 and J8.
For the PTN3310 to drive PTN3311, the input signal must be
connected to SMA J5 and SMA J6, with resistors R7 & R9, R8 &
R10, and R21 and R22 assembled on the board, whereas R5 & R6,
R13 & R14, and R15 & R16 should be dismounted. The output
signal could be viewed via SMAs J3 and J4.
For the two parts to be evaluated independently, all resistors, except
R8 and R10 should be mounted on the board. In this case the input
signal for the PTN3310 will be provided via SMAs J5 and J6, and for
the PTN3311 it will be via SMAs J1 and J2. The corresponding
outputs of the parts could be connected to oscilloscope through
SMAs J7 & J8 and J3 & J4 for PTN3310 and PTN3311 respectively.
In the following appendix, attached are:
? Bill of materials
? Schematic
? Top layer layout and silk screen
SUPPORT