The AS7C4096A is a high-performance CMOS 4，194，304-bit Static Random Access Memory （SRAM） device organized as 524，288 words × 8 bits. It is designed for memory applications where fast data access， low power， and simple interfacing are desired. Equal address access and cycle times （tAA， tRC， tWC） of 10/12/15/20 ns with output enable access times （tOE） of 5/6 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable （WE） and chip enable （CE）。 Data on the input pins I/O1–I/O8 is written on the rising edge of WE （write cycle 1） or CE （write cycle 2）。 To avoid bus contention， external devices should drive I/O pins only after outputs have been disabled with output enable （OE） or write enable （WE）。 A read cycle is accomplished by asserting output enable （OE） and chip enable （CE）， with write enable （WE） high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive， or write enable is active， output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible， and operation is from a single 5.0V supply voltage. This device is available as per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.