8

存儲(chǔ)器

8.5 外部存儲(chǔ)器

RA6 MCU包含用于連接到外部存儲(chǔ)器和器件的外部數(shù)據(jù)總線。某些產(chǎn)品還包括一個(gè)內(nèi)置的SDRAM控制器，可通過(guò)該控制器使用最高達(dá)128MB的外部SDRAM。八個(gè)可編程片選提供了許多選項(xiàng)，可以在每個(gè)片選上設(shè)置這些選項(xiàng)，以允許連接到各種外部器件。存儲(chǔ)器映射的外部片選區(qū)域地址從0x60000000開(kāi)始。有關(guān)更多詳細(xì)信息，請(qǐng)參見(jiàn)《硬件用戶手冊(cè)》。

8.5.1 使用外部16位存儲(chǔ)器器件

連接具有字節(jié)選擇線的外部16位存儲(chǔ)器器件時(shí)，將MCU的A1連接到存儲(chǔ)器的A0，將MCU的A0連接到字節(jié)選擇線。

8.5.2 SDRAM初始化示例

Renesas FSP提供了采用CMSIS數(shù)據(jù)結(jié)構(gòu)的C語(yǔ)言頭文件，此文件映射了所有外部總線控制寄存器。以下函數(shù)是在Renesas FSP中使用CMSIS寄存器結(jié)構(gòu)初始化SDRAM存儲(chǔ)器控制器的示例。

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void bsp_sdram_init (void)
{
  /** Delay at least 100uS after SDCLK active */ 
  R_BSP_SoftwareDelay(100U, BSP_DELAY_UNITS_MICROSECONDS);


  /** Setting for SDRAM initialization sequence */
#if (BSP_PRV_SDRAM_TRP < 3)
  R_BUS->SDRAM.SDIR_b.PRC = 3U;
#else
  R_BUS->SDRAM.SSDIR_b.PRC = BSP_PRV_SDRAM_TRP - 3U;
#endif


  while(R_BUS->SDRAM.SDSR)
  {
    /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
  }


  R_BUS->SDRAM.SDIR_b.ARFC = BSP_PRV_SDRAM_SDIR_REF_TIMES; 


  while(R_BUS->SDRAM.SDSR)
  {
    /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
  }


#if (BSP_PRV_SDRAM_TRFC < 3)
  R_BUS->SDRAM.SDIR_b.ARFI = 0U;
#else
  R_BUS->SDRAM.SDIR_b.ARFI = BSP_PRV_SDRAM_TRFC - 3U;
#endif


  while(R_BUS->SDRAM.SDSR)
  {
    /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */
  }


  /** Start SDRAM initialization sequence.
   * Following operation is automatically done when set SDICR.INIRQ bit.
   * Perform a PRECHARGE ALL command and wait at least tRP time.
   * Issue an AUTO REFRESH command and wait at least tRFC time.
   * Issue an AUTO REFRESH command and wait at least tRFC time.
   */
  R_BUS->SDRAM.SDICR_b.INIRQ = 1U; 
  while(R_BUS->SDRAM.SDSR_b.INIST)
  {
    /* Wait the end of initialization sequence. */
  }


  /** Setting for SDRAM controller */
  R_BUS->SDRAM.SDCCR_b.BSIZE = BSP_PRV_SDRAM_BUS_WIDTH;       /* set SDRAM bus width */
  R_BUS->SDRAM.SDAMOD_b.BE = BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE;  /* enable continuous access */
  R_BUS->SDRAM.SDCMOD_b.EMODE = BSP_PRV_SDRAM_ENDIAN_MODE;     /* set endian mode for SDRAM address space */


  while(R_BUS->SDRAM.SDSR)
  {
    /* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */
  }
  
  /** Using LMR command, program the mode register */
  R_BUS->SDRAM.SDMOD = ((((uint16_t)(BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC  << 9)
      |(uint16_t)(BSP_PRV_SDRAM_MR_OP_MODE     << 7))
      |(uint16_t)(BSP_PRV_SDRAM_CL         << 4))
      |(uint16_t)(BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL << 3))
      |(uint16_t)(BSP_PRV_SDRAM_MR_BURST_LENGTH  << 0);


  /** wait at least tMRD time */ 
  while(R_BUS-
  >SDRAM.SDSR_b.MRSST)
  {
    /* Wait until Mode Register setting done. */
  }


  /** Set timing parameters for SDRAM */
  R_BUS->SDRAM.SDTR_b.RAS = BSP_PRV_SDRAM_TRAS - 1U;  /* set ACTIVE-to-PRECHARGE command cycles*/
  R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U;  /* set ACTIVEto READ/WRITE delay cycles */
  R_BUS->SDRAM.SDTR_b.RP = BSP_PRV_SDRAM_TRP - 1U;  /* set PRECHARGE command period cycles */
  R_BUS->SDRAM.SDTR_b.WR = BSP_PRV_SDRAM_TWR - 1U;  /* set write recovery cycles */
  R_BUS->SDRAM.SDTR_b.CL = BSP_PRV_SDRAM_CL;     /* set SDRAM column latency cycles */


  /** Set row address offset for target SDRAM */
  R_BUS->SDRAM.SDADR_b.MXC = BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET - 8U;


  R_BUS->SDRAM.SDRFCR_b.REFW = (uint16_t)(BSP_PRV_SDRAM_TRFC - 1U);  /* set Auto-Refresh issuing cycle */
  R_BUS->SDRAM.SDRFCR_b.RFC = BSP_PRV_SDRAM_REF_CMD_INTERVAL - 1U;  /* set Auto-Refresh period */


  /** Start Auto-refresh */
  R_BUS->SDRAM.SDRFEN_b.RFEN = 1U;


  /** Enable SDRAM access */
  R_BUS->SDRAM.SDCCR_b.EXENB = 1U;
}

8.6 數(shù)據(jù)對(duì)齊

沒(méi)有對(duì)齊數(shù)據(jù)方面的限制。MCU能夠?qū)ζ鏀?shù)存儲(chǔ)地址執(zhí)行字節(jié)、字和長(zhǎng)整型訪問(wèn)。雖然對(duì)齊數(shù)據(jù)訪問(wèn)仍然是最佳選擇，但并不是必須的。

8.7 字節(jié)順序限制

存儲(chǔ)器空間必須采用小尾數(shù)法才能在Cortex-M內(nèi)核上執(zhí)行代碼。

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