原文鏈接：學(xué)verilog 一個月了，在開發(fā)板上面寫了很多代碼，但是始終對一些問題理解的不夠透徹，這里我們來寫幾個例子仿真出阻塞和非阻塞的區(qū)別，我們先上代碼module LED ?(??? CLK, RSTn,??? scan,??? flag ,??? c,??? ,one,two,three,four);???? input CLK;???? input RSTn;???? input scan;???? output flag,c;???? output [3:0] one,two,three,four;/***********************************************************/??????? reg F1,F2;??? reg a,b;??? reg [3:0] one,two,three,four;?/********************信號傳遞之間的非阻塞賦值***************************************/??? always @ ( posedge CLK or negedge RSTn ) ??//????? if( !RSTn )???????? begin?????????? F1 <= 1'b1;?????????? F2 <= 1'b1;????? end????? else??begin???F1 <= scan;???F2 <= F1;????? end?/*******************信號傳遞之間的阻塞賦值****************************************/??? always @ ( posedge CLK or negedge RSTn ) ??//????? if( !RSTn )???????? begin?????????? a = 1'b1;?????????? b = 1'b1;????? end????? else??begin???a = scan;???b = a;????? end?/******************數(shù)據(jù)加? 非阻塞賦值? 先判斷后計數(shù)*****************************************/??????always @ ( posedge CLK or negedge RSTn )?? //one <=??if( !RSTn )???begin????one<=0;???end??else??begin???if(one==14)???????one<=0;???else ?????????one<=one+1;??end/***************數(shù)據(jù)加? 非阻塞賦值? 先計數(shù)后判斷********************************************/ ???always @ ( posedge CLK or negedge RSTn )??? //? two<=??if( !RSTn )???begin????two<=0;???end??else??begin???two<=two+1;???if(two==14)????two<=0;??end?/**************數(shù)據(jù)加? 阻塞賦值? 先判斷后計數(shù)*********************************************/?always @ ( posedge CLK or negedge RSTn ) ?//three =??if( !RSTn )???begin????three=0;???end??else??begin???if(three==14)????three=0;???else????three=three+1;??end/*************數(shù)據(jù)加? 阻塞賦值? 先計數(shù)后判斷**********************************************/?always @ ( posedge CLK or negedge RSTn ) ?//four =??if( !RSTn )???begin????four=0;???end??else??begin???four=four+1;???if(four==14)????four=0;??end????????????/****************信號之間傳遞***********************/?assign flag = F2 & !F1;assign c ?= b? & !a;/***************************************/?endmodule ?????2、我使用modesim 仿真，下面為我的? test bench?`timescale 1 ps/ 1 psmodule LED_vlg_tst();// constants??????????????????????????????????????????// general purpose registersreg eachvec;// test vector input registersreg CLK;reg RSTn;reg scan;// wires??????????????????????????????????????????????wire c;wire flag;wire [3:0]? four;wire [3:0]? one;wire [3:0]? three;wire [3:0]? two;// assign statements (if any)?????????????????????????LED i1 (// port map - connection between master ports and signals/registers???.CLK(CLK),?.RSTn(RSTn),?.c(c),?.flag(flag),?.four(four),?.one(one),?.scan(scan),?.three(three),?.two(two));/*initial???????????????????????????????????????????????begin?????????????????????????????????????????????????// code that executes only once???????????????????????// insert code here --> begin???????????????????????????????????????????????????????????????????????????????// --> end????????????????????????????????????????????$display("Running testbench");??????????????????????end???????????????????????????????????????????????????always????????????????????????????????????????????????// optional sensitivity list??????????????????????????// @(event1 or event2 or .... eventn)?????????????????begin?????????????????????????????????????????????????// code executes for every event on sensitivity list??// insert code here --> begin???????????????????????????????????????????????????????????????????????????????@eachvec;?????????????????????????????????????????????// --> end????????????????????????????????????????????end???????????????????????????????????????????????????endmodule*/initial beginCLK = 0;forever#10 CLK = ~CLK;?endinitial beginscan = 0;forever#100 scan = ~scan;?endinitial beginRSTn = 0;#1000 RSTn =? 1;#1000;#1000;#1000;#1000;#1000;#1000;#1000;#1000;$stop;endendmodule?主要就是初始化一個CLK 和scan的信號，然后就是初始化一下復(fù)位，最后就是設(shè)置仿真時間，這樣modesim 就不會一直處于仿真狀態(tài)，消耗資源，也可以方便仿真。?其中quartus? 與modesim? 互相調(diào)用調(diào)試，可以關(guān)注我的博客，這里我就不具體講解了！?3、modesim 波形圖??大家注意到紅線框內(nèi)的數(shù)據(jù)變化，就能很清楚的理解 阻塞與非阻塞了！??微觀分析 阻塞與非阻塞1、上代碼，具體觀察，a,b,c與F1，F(xiàn)2，flage 的變化?module LED??(??? CLK, RSTn,??? scan,??? flag ,??? a,b,c,F1,F2,);???? input CLK;???? input RSTn;???? input scan;???? output flag,a,b,c;???? output F1,F2;/***********************************************************/??????? reg F1,F2;??? reg a,b;?/***********************************************************/??? always @ ( posedge CLK or negedge RSTn ) ??//????? if( !RSTn )???????? begin?????????? F1 <= 1'b1;?????????? F2 <= 1'b1;????? end????? else??begin???F1 <= scan;???F2 <= F1;????? end?/***********************************************************/??? always @ ( posedge CLK or negedge RSTn ) ??//????? if( !RSTn )???????? begin?????????? a = 1'b1;?????????? b = 1'b1;????? end????? else??begin???a = scan;???b = a;????? end?/***********************************************************/??????assign flag = F2 & !F1;assign c ?= b? & !a;/***************************************/?endmodule ????代碼涵義就不講解了?2、test bench 代碼，與上面相同，這里不重復(fù)了?3、上圖?? 看波形