In Chapter 3 many issues related to the operation and use of the central code of the DSP

　　processor were introduced. In particular the operation of the ALU， hardware multiplier，

　　various registers， control registers and the accumulator were all considered. In this section

　　we move on to consider the other facilities typically found on a DSP device. Figure 4.1

　　shows the hypothetical DSP device introduced in the previous chapter. As already mentioned we will use this device again as the basis for our discussion and as with Chapter 3

　　we will relate the generic DSP features presented in the hypothetical device with examples

　　taken from real devices.

　　In Figure 4.1， the central core is shown at the center of the DSP device. In this section

　　we will consider the components arranged outside the core but still inside the DSP device

　　itself. Most of these components are able to run in parallel with the DSP core， taking little

　　of the core’s available instruction cycle time. A good example of this is the on-chip timer

　　which can be initialized to interrupt the DSP device at a regular rate， e.g. every 1 ms. If the

　　timer was not available this task would be carried out using a software routine which

　　would directly impact on the core itself. By delegating tasks to on-chip components， the

　　processing core can be freed up to handle the more demanding arithmetic requirements

　　of the algorithm. Of course at start-up， when the DSP is reset， all of the peripheral components must be initialized and set to a known state. This has already been considered a

　　little in Section 2.2.1， although initialization issues will also be considered further here.

　　We start by looking at each of the components shown in Figure 4.1， as follows.