Pushing the Limits of Packaging

　　微控制器的封裝在系統(tǒng)的小型化中起著關(guān)鍵作用。對(duì)外圍設(shè)備的選擇上的權(quán)衡，墊計(jì)數(shù)和芯片尺寸都限制了能力，以減少微控制器的大小，但仍有助于減少終端設(shè)備的整體尺寸。

　　熱的問(wèn)題也很重要，考慮到微控制器得到更小的尺寸。在較小的芯片上有更多的晶體管，在更高的頻率運(yùn)行，功耗是一個(gè)關(guān)鍵的考慮因素。同時(shí)降低電壓和門(mén)控不同的外設(shè)，使未使用的元素不消耗功率，可以減少整體的熱負(fù)荷，多余的熱量產(chǎn)生，然后必須有效地刪除或微控制器將降級(jí)，最終失敗。這是一個(gè)關(guān)鍵的可靠性問(wèn)題，必須考慮小型單片機(jī)系統(tǒng)。

　　這是引腳與大小的權(quán)衡進(jìn)來(lái)。在封裝上的附加引腳可用于連接到熱過(guò)孔，從微控制器和其他設(shè)備，可能是敏感的溫度升高，如無(wú)線接口帶走多余的熱量。

　　While the latest chip-scale packaging can reduce the overall footprint of a device with a given functionality， reducing the area taken up by a quarter， the opportunity to integrate more peripherals into a device and have more pins for thermal dissipation may be more important.

　　The designer also has to be aware of the aim of miniaturization. An ARM 32-bit core， such as the Cortex-M0+ or even the M4， is less than a square millimeter of silicon – the size of the die is determined more by the amount of memory on chip and， vital for the packaging consideration， the peripherals that need to connect to the outside world. The smallest M0 devices， such as Freescale’s Kinetis KL02， can be as small as 1.9 x 2.0 mm in a chip-scale package that is barely larger than the die itself. At less than 4 square millimeters， this occupies twenty-five percent less PCB area than ball grid array or LGA packages but provides sixty percent more GPIO with up to twenty-eight lines. This move， almost ‘silicon dust’， allows designers to dramatically reduce their board size without compromising the performance， feature integration and power consumption of the end products.