The AS7C1024B is a high performance CMOS 1，048，576-bit Static Random Access Memory （SRAM） device organized as 131，072 words x 8 bits. It is designed for memory applications where fast data access， low power， and simple interfacing are desired. Equal address access and cycle times （tAA， tRC， tWC） of 10/12/15/20 ns with output enable access times （tOE） of 5/6/7/8 ns are ideal for high performance applications. Active high and low chip enables （CE1， CE2） permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low， the devices enter standby mode. If inputs are still toggling， the device will consume ISB power. If the bus is static， then full standby power is reached （ISB1）。 For example， the AS7C1024B is guaranteed not to exceed 55 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable （WE） and both chip enables （CE1， CE2）。 Data on the input pins I/O0 through I/O7 is written on the rising edge of WE （write cycle 1） or the active-to-inactive edge of CE1 or CE2 （write cycle 2）。 To avoid bus contention， external devices should drive I/O pins only after outputs have been disabled with output enable （OE） or write enable （WE）。 A read cycle is accomplished by asserting output enable （OE） and both chip enables （CE1， CE2）， with write enable （WE） high. The chips drive I/ O pins with the data word referenced by the input address. When either chip enable is inactive， output enable is inactive， or write enable is active， output drivers stay in high-impedance mode.
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