This paper presents a unified processor core with two operation modes. The processor core
works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW core in the DSP mode, which has the distributed and ping-pong register organization optimized for
stream processing. To minimize the hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the proposed hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor core has been implemented in the UMC 0.18μm CMOS technology, and its core size is 3.23mm×3.23μm ncluding the 32KB on-chip memory. It can operate at 208MHz, while consuming 380.6mW average power.