Frequency synthesizers are critical components of all communication systems. A frequency synthesizer generates the local oscillator （LO） signal used by mixers to upconvert a baseband signal in a transmitter and down-convert the RF signal to baseband in a receiver. Synthesizers also supply the clock signal that runs the digital systems. There are two types of frequency synthesizer architectures： indirect and direct. The indirect architecture has a feedback loop such as a phase locked loop （PLL）。 Traditional direct frequency synthesis uses a phase counter， a sine look-up table and a digital-toanalog （DAC） converter. This thesis considers the issue of undesirable frequency spurs of a relatively recent type of direct frequency synthesis architecture called digital-to-time conversion （DTC）。 The DTC-based frequency synthesis architecture has important performance benefits over older frequency synthesizers， such as fast frequency switching， large frequency range and high frequency resolution. A DTC-based frequency synthesizer requires less power than a traditional direct synthesis based synthesizer with comparable frequency range， resolution and switching time. The DTC architecture is also easily scalable to newer low-cost digital complementary metal-oxide-semiconductor （CMOS） integrated circuit （IC） fabrication technologies. However， the DTC architecture suffers from an important undesirable characteristic